Memory Testing: MBIST, BIRA & BISR | An Insight into Algorithms and Self Repair Mechanism

Typically, we see a 4X increase in memory size every 3 years to cater to the needs of new-generation IoT devices. Deep submicron devices contain a large number of memories which demands lower area and fast access time, hence, an automated testing strategy for such semiconductor engineering designs is required to reduce ATE (Automatic Test Equipment) time and cost.

Memory faults behave differently than classical Stuck-At faults. Therefore, the fault models are different in memories (due to their array structure) than in the standard logic design. Also, during memory tests, apart from fault detection and localization, self-repair of faulty cells through redundant cells is also implemented.

It is also a challenge to test memories from the system design level as it requires test logic to multiplex and route memory pins to external pins. To test the memories functionally or via ATPG (Automatic Test Pattern Generation)requires very large external pattern sets for acceptable test coverage due to the size and density of the cell array and its associated faults.

Know More@ https://www.einfochips.com/blog/memory-testing-an-insight-into-algorithms-and-self-repair-mechanism/

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